SV interview questions

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Qi1)What is callback ?

(Qi2)What is factory pattern ?

(Qi3)Explain the difference between data types logic and reg and wire .

(Qi4)What is the need of clocking blocks ?

(Qi5)What are the ways to avoid race condition between testbench and RTL using SystemVerilog?

(Qi6)Explain Event regions in SV.

(Qi7)What are the types of coverages available in SV ?

(Qi8)What is OOPS?

(Qi9)What is inheritance and polymorphism?

(Qi10)What is the need of virtual interfaces ?

(Qi11)Explain about the virtual task and methods .

(Qi12)What is the use of the abstract class?

(Qi13)What is the difference between mailbox and queue?

(Qi14)What data structure you used to build scoreboard?

(Qi15)What are the advantages of linkedlist over the queue ?

(Qi16)How parallel case and full cases problems are avoided in SV ?

(Qi17)What is the difference between pure function and cordinary function ?

(Qi18)What is the difference between $random and $urandom?

(Qi19)What is scope randomization ?

(Qi20)List the predefined randomization methods.

(Qi21)What is the dfference between always_combo and always@(*)c?

(Qi22)What is the use of packagess?

(Qi23)What is the use of $cast?

(Qi24)How to call the task which is defined in parent object into derived class ?

(Qi25)What is the difference between rand and randc?

(Qi26)What is $root?

(Qi27)What is $unit?

(Qi28)What are bi-directional constraints?

(Qi29)What is solve...before constraint ?

(Qi30)Without using randomize method or rand,generate an array of unique values?

(Qi31)Explain about pass by ref and pass by value?

(Qi32)What is the difference between
bit[7:0] sig_1;
byte sig_2;

(Qi33)What is the difference between program block and module ?

(Qi34)What is final block ?

(Qi35)How to implement always block logic in program block ?

(Qi36)What is the difference between fork/joins, fork/join_none fork/join_any ?

(Qi37)What is the use of modports ?

(Qi38)Write a clock generator without using always block.

(Qi39)What is forward referencing and how to avoid this problem?

(Qi40)What is circular dependency and how to avoid this problem ?

(Qi41)What is cross coverage ?

(Qi42)Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them

(Qi43)How to kill a process in fork/join?

(Qi44)Difference between Associative array and Dynamic array ?

(Qi45)Difference b/wProcedural and Concarent Assertions?

(Qi46)What are the advantages of SystemVerilog DPI?

(Qi47)how to randomize dynamic arrays of objects?

(Qi48)What is randsequence and what is its use?

(Qi49)What is bin?

(Qi50)
Initial
wait_order(a,b,c);

Which from below initial process will cause that above wait order will pass.
a)
ig initial begin
#1;
->a;
->b;
->c;
end

b)
initial begin
#1;
->a;
end
always @a->b;
always(at)b-> c;

c)

initial begin
#1;
->a;
#0 ->b;
->>c;
end

d)

initial begin
#1 ->a;
#1 ->b;
#1 ->c;
end


(Qi51)Why always block is not allowed in program block?

(Qi52)Which is best to use to model transaction? Struct or class ?

(Qi53)How SV is more random stable then Verilog?

(Qi54)Difference between assert and expect statements?

(Qi55)How to add a new processs with out disturbing the random number generator state ?

(Qi56)What is the need of alias in SV?

(Qi57)What would be the output of the following code and how to avoid it?
for(int i=0; i 1?
Ans:=>

(Qi62)What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?

(Qi63)How different is the implementation of a struct can union in SV.

(Qi64)What is "this"?

(Qi65)What is tagged union ?

(Qi66)What is "scope resolution operator"?


(Qi67)What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?


(Qi68)What is the difference between
logic data_1;
var logic data_2;
wire logic data_3j;
bit data_4;
var bit data_5;

(Qi69)What is the difference between bits and logic?

(Qi70)Write a Statemechine in SV styles.

(Qi71)What is the difference between $rose and posedgec?

(Qi72)What is advantage of program block over clockcblock w.r.t race condition?

(Qi73)How to avoid the race condition between programblock ?

(Qi74)What is the difference between assumes and assert?

(Qi75)What is coverage driven verification?

(Qi76)What is layered architecture ?

(Qi77)What are the simulation phases in your verification environment?

(Qi78)How to pick a element which is in queue from random index?

(Qi79)What data structure is used to store data in your environment and why ?

(Qi80)What is casting? Explain about the various types of casting available in SV.

(Qi81)How to importuall the items declared inside a package ?

(Qi82)Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?

(Qi83)What is streaming operator and what is its use?

(Qi84)What are void functions ?

(Qi85)How to make sure that a function argument passed has ref is not changed by the function?

(Qi86)What is the use of "extern"?

(Qi87)What is the difference between initial block and final block?
Ans:

You can't schedule an event or have delays in final block.


(Qi88)How to check weather a handles is holding object or not ?

(Qi89)How to disable multiple threads which are spawned by fork...join

SV中join_any和join_none的使用情景

join_any是指父进程进入等待状态，直到有一个子进程完成。一旦有一个子进程完成，那么父进程也就继续往下进行，但是其他的子线程依然在队列中，并不会消失，因此，fork-join_any后面通常会有一条杀掉其他子进程的语句（disable fork)。由于join_any的这种特性，因此经常用于看门狗的设计。如下面语句：
fork: frameo_wd_timer
@(negedge router.cb.frameo_n[da]);
begin
repeat(1000) @(router.cb);
$display("\n%m\n[ERROR]%t Frame signal timed out!\n", $realtime);
$finish;
end
join_any: frameo_wd_timer
disable frameo_wd_timer;

join_none是指父进程根本不等自进程，继续往下执行，此时的子进程在队列中排队等待，直到父进程遇到阻塞性的语句,即wait,#,@。不包括阻塞性的赋值语句（a = 1'b1)。如下面的语句：
program automatic test;
reg a;
initial
begin
fork
begin
#2;
$display("%t:state1",$time);

end
begin
$display("%t:state2",$time);
#2;
end
join_none
$display("%t:state3",$time);
$display("%t:state4",$time);
a =1'b1;
$display("%t:state4.1",$time);
fork
begin
$display("%t:state5",$time);
#2;
end
begin
$display("%t:state6",$time);
#2;
end
join_none
$display("%t:state7",$time);
wait fork;
end
endprogram
在VCS中执行结果为；
0:state3
0:state4
0:state4.1
0,state7
0:state2
0:state5
0:state6
2:state1
由于fork-join_none的不阻塞特性，经常用于monitor进程观测对象，也用于产生很多独立的激励进程。如下面的语句：
task Generator::start();
if (TRACE_ON) $display("[TRACE]%t %s:%m", $realtime, name);
fork
for (int i=0; i<= 0; i++) begin
gen();
begin
Packet pkt = new pkt2send;
out_box[pkt.sa].put(pkt);
end
end
join_none
endtask

SV中mailbox的使用

下面为学习mailbox写的一个简单的sv代码，主要功能是一方发送随机数量的packet，一方接收该packet，两者的channel使用mailbox来实现。在questasim 6.5版本上编译通过，仿真通不过，具体的原因是questasim对mailbox的内容要求为packed类型。在VCS 200812版本上编译通过，仿真通过。
program automatic test_mailbox;
timeunit 1ns;
timeprecision 1ps;
int run_for_n_pkt = 10;

class packet;
rand bit [3:0] addr;
rand bit [7:0] din;
rand reg [7:0] payload[];

function new();
endfunction

constraint pkt_ct {
addr dist {[0:3] :=40,[4:7] :=60};
din inside {[0:$]};
payload.size() inside {[2:4]};
foreach(payload[i])
payload[i] == i;
}
endclass

class tx_pkts;
string name;
int num_pkt;
packet tx_pkt;
mailbox tx_mbx;

function new(string name = "TXP" ,mailbox tx_mbx = null,int num_pkt);
this.name = name;
this.tx_mbx = tx_mbx;
if(num_pkt <= 0 )
this.num_pkt = 1;
else
this.num_pkt = num_pkt;
endfunction

function void display();
$display("tx_pkt name is %s",name);
endfunction

task send_pkts();
fork
for(int i=0 ; i< num_pkt ;i++)
begin
packet temp_pkt;
temp_pkt = new();
if(!(temp_pkt.randomize()))
begin
$display("%t : randomize failed,please check your svtb! :%m",$realtime);
$finish;
end
tx_mbx.put(temp_pkt);
$display("transmitting data at %t:\n",$realtime);
$display("addr = %4b ; din = %8b;",temp_pkt.addr,temp_pkt.din);
foreach(temp_pkt.payload[j])
$display("payload[%d] = %2h;",j,temp_pkt.payload[j]);
#3;
end
join_none
endtask
endclass

class rx_pkts;
event done;
string name;
int num_pkt;
packet rx_pkt;
mailbox rx_mbx;

function new(string name = "RXP",mailbox rx_mbx = null);
this.name = name;
this.rx_mbx = rx_mbx;
this.num_pkt = 0;
endfunction

task receive_pkts();
fork
while(1)
begin
packet temp_pkt;
rx_mbx.get(temp_pkt);
$display("receiving data at %t:\n",$realtime);
$display("addr = %4b ; din = %8b;",temp_pkt.addr,temp_pkt.din);
foreach(temp_pkt.payload[j])
$display("payload[%d] = %2h;",j,temp_pkt.payload[j]);
num_pkt++;
if(num_pkt >= run_for_n_pkt)
->done;
end
join_none
endtask
endclass

initial
begin
mailbox p_mbx;
tx_pkts txp;
rx_pkts rxp;
p_mbx = new();
txp = new("INTEL",p_mbx,run_for_n_pkt);
rxp = new("VIMICRO",p_mbx);
#10;
txp.send_pkts();
rxp.receive_pkts();
wait(rxp.done.triggered);
end

endprogram

语音信号处理中几个电平的含义

1.绝对功率电平

通常是以1mw为基准功率，相对与1mw的功率电平称之为绝对功率电平，其电平符号为dBm，比如20W的功率输入，就可以认为输入电平是10*log（20W/1mW) ,即43dBm。0dBm表示1mw的输入电平，这一毫瓦基准值是在600欧姆（Ω）的电阻上耗散的一毫瓦功率，此时电阻上的电压有效值为0.775伏(V)，所流过的电流为1.291毫安（mA）。取作基准值的1mW，0.775V，1.291mA分别称为零电平功率，零电平电压和零电平电流。 注意一下就是dB不要写成DB，db等等其他形式，这个已经成为ITU的规范。

2.相对功率电平
不使用固定的功率作为比较的基准，而是以参考点的信号功率为比较对象，这样求得的电平称为相对功率电平，其电平符号为dBr。

3.TLP

全称为transmission level point，即传送电平点，这是为了简化电路设计引入的一个概念，比如一个点，定义为0TLP，经过3db的衰减后到了另一个点，那么这个点的TLP值就为-3TLP。

4.dBm0

dBm0的含义同dBm类似，只是相对于零TLP点的dBm值。还是很难理解是把，看下面的图就明白了。


所以一个参考点的dBm0值的计算方法如下：Value(dBm0) = Value(dBm) - Value(TLP)；所以在一个电路中不管经过怎么样的衰减还是放大，各个点的dBm0都是一样的。

VCS2008在ubuntu上的安装

今天不上班，在家休息之余，装了个VCS2008，跑跑小仿真玩玩。在公司里仿真器都是采用cadence的ldv5.1，版本比较老，对systemverilog的支持比较弱，加上目前还找不到ius的仿真器，于是还是搞俺的VCS吧。

ubuntu版本：8.04
VCS版本：2008.12

安装过程采用synopsys推荐的标准安装方法，采用synopsys installer V1.8安装tar文件，然后就是设置环境变量，由于之前安装DC的时候license生成，并且指定好，所以这一步可以简化，只需要指定VCS_HOME环境变量。最后就是指定路径哈，比较简单。这些做完之后，试了一下在console中敲入vcs tb.v，结果通常会让人感到郁闷。
1.首先是一个linux内核的warning,实际上不影响最后的功能，为了每次不报告出warning，还是设置了一下环境变量:setenv VCS_ARCH_OVERRIDE linux
2.编译的时候stdio.h的文件找不到。查看了一下/usr/include内容，确实是没有该头文件，安装下面文件即可 sudo apt-get install build-essential
3.在链接文件的时候，提示lz错误，应该是缺少libz.a或者是libz.so文件，从网上download一个zlib的文件，tar解压后，使用./configuire来配置，并且make安装。安装完毕后可以在/usr/local/lib里发现多了一个libz.a文件，正是所需要的。

一切完毕之后编译链接都过了，产生一个simv文件，然后调用simv -gui，ok～，一切搞定，目前还没有发现其他的问题。

set_ideal_network 和set_dont_touch_network的使用总结

set_ideal_network用来对port，pin，net来设置ideal_network属性，所谓的ideal_network属性就是0电阻0电容+所有的cell和net都dont_touch。因此就会0转换时间，0延时，综合优化的时候不会对路径的cell和net进行优化。

注意：1.对net进行设置的时候，必须要带上no_propagate的属性，否则是加不上去的。对port和pin可以加上带也可以不带no_propagate。2.当ideal_network经过一个组合logic的时候，只有当所有的输入都具有ideal属性，并且至少有一半具有传播的属性，即不带-no_propagate，输出端才有ideal_net属性。3.在定义时钟的时候，默认是具有这个属性的，但是要注意的是，当时钟网络上具有多输入组合逻辑的时候，时钟的ideal_net属性是不会穿过这个组合逻辑的。比如一个2in1 mux，输出端就不具备ideal_net属性，延时就会计算进去。所以定义时钟的时候最好还是加上这条命令。

set_dont_touch_network用来对port，pin，clock来设置dont_touch_network的属性。所谓的dont_touch_network属性就是在优化的时候，不会对原有的器件进行替换。

tcl在DC中的使用-----part2

1.如何查询当前design的registers占leaf cell的比重呢？

registers数目可以用all_registers来得到，下面为tcl脚本：

set leafcells [get_cells *]

set flops [all_registers]

set cnt_leaf [size_of_collection $leafcells]

set cnt_flops [size_of_collection $flops]

set precentage [expr 100.0 * $cnt_flops / $cnt_leaf]

unset flops

实际上all_registers可以用另一种方法得到：

get_cells * -filter "is_sequential == true"，在filter中常用的操作符有 == =~ !~ defined() undefined()。

2 timing path的深入操作上面标出了timing path最常用的七个属性，注意不能用get_object_name来对某条timing path在操作，因为timing path没有name的属性。只有具有name属性的单个对象的集合才可以使用get_object_name或者get_attribute XXX full_name。所以get_timing_paths要结合get_attribute使用。另外需要注意的是使用get_attribute得到的属性也有可能是一个集合，糊涂了是把。看看下面的例子：
get_timing_paths有很多的option，基本上和report_timing的option是一样的。因此用起来很方便。